Low voltage AC power signals, i.e., up to approximately 1 kV, are typically synthesized using conventional power converters which employ insulated gate bipolar transistor (IGBT) switching devices. The switching devices are connected together in a bridge configuration and are controlled to synthesize a single phase or multi-phase AC output signal at a selected frequency and voltage, current, or power level from either a DC signal or an AC signal at a different frequency or at a different voltage, current, or power level. IGBT switching devices may be modulated at a high frequency, e.g., 10-20 kHz, which is typically well above the fundamental frequency of the AC output waveform being synthesized. Pulse width modulation or other similar high frequency modulation techniques may thus be used to control the IGBT switching devices in conventional power converters. The spectral performance of conventional power converters is typically excellent due to this high frequency modulation of the converter switching devices. High frequency modulation of the switching devices in the conventional power converter allows a nearly sinusoidal AC output waveform to be generated which, with minimal passive filtering on the output of the converter, includes very little harmonic, i.e., non-fundamental, frequency content.
Conventional power converters employing IGBT switching devices cannot be used, however, to synthesize high voltage output signals, beyond about 2 kV. This limitation is due to the limited voltage blocking capability, less than 1.5 kV, of most commercially available IGBTs. For high output voltage levels, up to 5 kV, converters employing gate turn-off (GTO) thyristor switching devices can be used. GTO thyristors have much higher voltage blocking capability than IGBTs. However, the switching capability of GTO thyristors is limited. GTO thyristors typically cannot be switched at a frequency much higher than the fundamental frequency of the output signal to be synthesized. Thus, the spectral performance of a high voltage converter employing GTO thyristors is limited. A GTO thyristor converter can only provide harmonic performance similar to an IGBT based converter if an immense, and typically prohibitive, amount of filtering is employed.
There is a growing demand for high voltage power conversion systems capable of providing high voltage output signals and having good spectral performance and control. For example, such a system would be a useful power supply for high voltage electric powered traction locomotives and other transportation systems which are currently in operation in Europe and which are planned for introduction in the United States. Another application for high voltage power conversion systems is harmonic compensation and active filtering in electric power distribution systems. Certain industrial customers of electric power utilities can produce harmonics in the entire electric distribution system. Such harmonics can damage distribution equipment, require the overrating of such equipment, and adversely affect the operations of other industrial customers of the utility. An example of such a "dirty load" is a steel mill operation, wherein rectifiers are used to develop DC bus voltages used in the mill. The switching frequency of the rectifiers can be reflected back onto the power lines providing power to the mill, thereby generating harmonics in the power distribution system. A passive filtering system, composed of capacitors and inductors, may be used to reduce the harmonics fed back into the power distribution system from such a load. However, it has been found that an inverter, either by itself or in combination with passive filtering components, may be controlled to provide harmonic compensation and filtering of such loads. Such "active filtering" can be highly effective in eliminating harmonics from the electric power distribution system. Unlike purely passive filter components, an active filter inverter can be controlled dynamically to respond to changing conditions on the electric power distribution system. It is apparent that, for high voltage active filtering applications in particular, a high voltage power converter having good and controllable spectral performance is required.
A known method for achieving high output voltage levels from a power conversion system is to employ a multilevel power converter topology. The number of converter levels required in any such multilevel topology depends on the output voltage level desired and the type of switching devices employed in the converter. Higher voltage levels can be achieved with fewer converter levels if GTO thyristors are employed in the converter. However, a multilevel converter employing GTO thyristors will have poor spectral performance. Alternatively, a greater number of converter levels, with IGBT switching devices employed in each level, may be employed to achieve a high voltage output level without sacrificing spectral performance. However, increasing the number of converter levels also increases converter circuit control complexity and cost.
An example of a known multilevel converter topology is the diode clamped inverter. An exemplary diode clamped multilevel inverter 20 is illustrated in, and will be described with reference to, FIG. 1. FIG. 1 illustrates a single phase of a three phase diode clamped multilevel inverter. The remaining two phases will have a similar configuration, and share the same DC bus. The exemplary diode clamped inverter 20 includes four DC bus capacitors 22-25 connected in series to form a quadruple DC bus. All of the capacitors 22-25 are identical, and the DC voltage level across each of the capacitors 22-25 is equal. In the present example, the voltage level across each capacitor 22-25 is 2.65 kV. Eight inverter switching devices, 27-34, hereinafter S.sub.1 -S.sub.8, are individually connected in series. The group of series connected switching devices S.sub.1 -S.sub.8 is connected across the series connected DC bus capacitors 22-25. In this case, each switching device 27-34 is implemented as a GTO thyristor 36 and a diode 38 connected in anti-parallel with the GTO thyristor 36. Five tapping points A.sub.1-5 are defined along the quadruple DC bus. Tapping points A.sub.1 and A.sub.5 are at the ends of the quadruple DC bus, and tapping points A.sub.2, A.sub.3 and A.sub.4 are defined at the connecting points between capacitors 22 and 23, 23 and 24, and 24 and 25, respectively. Clamp diodes 40-45 are connected between the tapping points A.sub.2, A.sub.3 and A.sub.4 along the quadruple DC bus and selected points between the series connected switching devices 27-34. Clamp diodes 40 and 41 are connected between tapping point A.sub.2 and points between switching devices S.sub.1 and S.sub.2, and S.sub.5 and S.sub.6, respectively. Clamp diodes 42 and 43 are connected between tapping point A.sub.3 and points between switching devices S.sub.2 and S.sub.3, and S.sub.6 and S.sub.7, respectively. Clamp diodes 44 and 45 are connected between tapping point A.sub.4 and points between switching devices S.sub.3 and S.sub.4, and S.sub.7 and S.sub.8, respectively.
It may be observed from FIG. 1 that a five-level output waveform can be synthesized at output node A, between switching devices S.sub.4 and S.sub.5, by tapping the five tapping points A.sub.1-5 on the quadruple DC bus. Thus, the diode clamped inverter circuit can be thought of as a multiplexer, with switching devices S.sub.1 -S.sub.8 for connecting the output node A to one of five available voltage levels. A peak voltage of, in this case, +/-5.3 kV can be realized by clamping the output node A to the top tapping point A.sub.1 or bottom tapping point A.sub.5 of the DC bus. This is accomplished by closing a set of four switches, either S.sub.1 -S.sub.4, or S.sub.5 -S.sub.8, for obtaining output voltage levels of +5.3 kV or -5.3 kV, respectively. The other three "inner" voltage levels, in this case, 2.65 kV, 0, and -2.65 kV, can be synthesized by closing switching devices S.sub.2 -S.sub.5, S.sub.3 -S.sub.6, or S.sub.4 -S.sub.7, respectively. This creates a current path connecting two of the clamp diodes cathode-to-anode. The other ends of these clamp diodes are connected to one of the voltage-taps A.sub.2, A.sub.3, or A.sub.4, along the DC bus. For example, to realize the 2.65 kV voltage level at the output A of the diode clamped inverter 20, switching devices S.sub.2 -S.sub.5 are closed, connecting the cathode of clamp diode 40 to the anode of clamp diode 41 at output node A. The anode of clamp diode 40 and cathode of clamp diode 41 are connected to tapping point A.sub.2 on the quadruple DC bus. Thus, with switching devices S.sub.2 -S.sub.5 closed, the voltage across DC bus capacitor 23 is connected, via clamp diodes 40 and 41, to the output node A. These diodes also prevent the undesired voltage levels across the other DC bus capacitors from being connected to the output node A.
It has been demonstrated that a diode clamped inverter topology can be used to synthesize three phase line-to-line AC voltage levels of up to 7.46 kV using 4.5 kV GTO thyristor switching devices. However, since, as discussed previously, the switching capability of GTO thyristors is limited at higher frequencies, the spectral performance of such a configuration is limited. IGBT switching devices may be employed in the diode clamped inverter topology to improve spectral performance. However, in order to achieve high output voltage levels using such switching devices, the diode clamped inverter topology must have numerous levels. Although the diode clamped inverter topology works well up to four or five levels, the topology becomes highly cumbersome and difficult to realize beyond this number of levels. It should be noted that the required reverse voltage blocking capability of the clamp diodes in the diode clamped inverter varies with the voltage level at which the diode is employed. Also, it has been demonstrated that for induction machine drive applications the DC bus of a diode clamped inverter is loaded non-uniformly, causing an additional problem of DC bus capacitor voltage balancing.
An example of a variation of the five-level diode clamped inverter topology 20 which provides a solution to the DC bus capacitor voltage balancing problem is the exemplary four-level diode clamped rectifier-inverter topology 50 illustrated in FIG. 2. A single phase of a multi-phase four-level diode clamped rectifier-inverter is illustrated. The remaining phases will have a similar configuration. In order to achieve capacitor voltage balancing, a diode clamp structure is employed on both rectifier and inverter sides of a DC bus. The four-level diode clamped rectifier-inverter 50 includes a triple DC bus formed of three DC bus capacitors 52-54 connected together in series. Rectifier side switching devices 56-61 and inverter side switching devices 62-67 are connected together in series across the triple DC bus. In this case, each switching device 56-67 may be implemented as an IGBT 68 with a diode 70 connected in anti-parallel with the IGBT 68. Rectifier side clamp diodes 72 and 73 are connected between a tapping point on the DC bus between DC bus capacitors 52 and 53 and points between rectifier side switching devices 56 and 57, and 59 and 60, respectively. Rectifier side clamp diodes 74 and 75 are connected between a tapping point on the DC bus between DC bus capacitors 53 and 54 and points between rectifier side switching devices 57 and 58, and 60 and 61, respectively. Inverter side clamp diodes 76 and 77 are connected between the tapping point on the DC bus between DC bus capacitors 52 and 53 and points between inverter side switching devices 62 and 63, and 65 and 66, respectively. Inverter side clamp diodes 78 and 79 are connected between the tapping point on the DC bus between DC bus capacitors 53 and 54 and points between inverter side switching devices 63 and 64, and 66 and 67, respectively.
The rectifier side switching devices 56-61 are controlled to provide rectification of an input voltage signal provided on input node Ain, between rectifier side switching devices 58 and 59, to ensure that a balanced voltage level V is maintained across each DC bus capacitor 52-54. The inverter side switching devices 62-67 are controlled in a manner similar to that of the switching devices in the five-level diode clamped inverter 20 discussed previously. In this case, a four-level waveform may be realized from the triple DC bus, which allows four distinct voltage levels, +2V, +V, -V, and -2V. A set of three of the inverter switching devices 62-67 is closed at any given time to connect the output node A.sub.out, between inverter side switching devices 64 and 65, to one of the four tapping point voltage levels along the triple DC bus. Switching devices 62-64 are closed to provide voltage level +2V at the output node A.sub.out, switching devices 63-65 are closed to provide voltage level +V at output node A.sub.out, switching devices 64-66 are closed to provide voltage level -V at output node A.sub.out, and switching devices 65-67 are closed to provide voltage level -2V at output node A.sub.out.
Although providing a solution to the problem of DC bus capacitor voltage balancing for induction machine drive applications, the four-level diode clamped rectifier-inverter topology 50 is limited by the other limitations of the diode-clamped inverter topology discussed previously. Although the switching devices 56-67 in such a topology may be implemented with IGBTs, which may be switched at a high switching frequency to provide good spectral performance, the use of IGBT switching devices limits the output voltage level of the converter. Numerous levels must be emloyed if IGBTs are to be used for high voltage level applications. The diode clamped topology makes it cumbersome and difficult to realize such a rectifier-inverter beyond four or five levels. Higher output voltage levels can be achieved with fewer inverter levels if GTO thyristor switching devices are employed in the converter topology. However, the limited switching capability at high frequency of GTO thyristors will result in a converter which has poor spectral performance.
As discussed previously, in multilevel diode clamped inverter topologies the required voltage blocking capability of the clamp diodes varies with the level at which the diodes are employed in the circuit topology. Thus, multiple clamp diodes connected in series may be required at higher voltage levels. In order to avoid this requirement, an alternative multilevel inverter structure where the voltage across an open switch is constrained by clamping capacitors, instead of clamp diodes, has been proposed. These inverters are commonly known as flying capacitor inverters. Flying capacitor topology inverters, however, suffer from the other limitations of diode clamped inverter topologies. Poor spectral performance will result if GTO thyristor devices are used to implement the switching devices in the flying capacitor inverter topology. Better spectral performance can be achieved if IGBTs are used for the flying capacitor inverter switching devices. However, once again, numerous levels of IGBT switching devices must be employed to synthesize high voltage level output signals. Although the flying capacitor inverter topology works well for topologies having up to four or five voltage levels, the flying capacitor inverter topology is highly cumbersome to scale for more than this number of levels.
Multiple single phase inverters may be used to synthesize multilevel waveforms. Using multiple single phase inverters to synthesize multilevel waveforms was initially realized through phase shifting of multiple single phase inverter output voltage waveforms and adding the phase shifted waveforms vectorially using series connected transformer windings. However, when the number of phases increases beyond three or five, this approach becomes difficult to realize due to the requirement of multiple transformer windings.
As an alternative approach, a series connection of multiple single phase *inverters with multiple dedicated DC buses may be used to realize multilevel output waveforms. An example of such a modular approach for synthesizing multilevel waveforms is the H-bridge multilevel inverter. An exemplary known modular H-bridge multilevel inverter circuit topology 80 is illustrated in FIG. 3. In the H-bridge multilevel inverter approach, a number of full bridge single phase inverters, with dedicated isolated DC bus capacitors/voltage sources, are connected together in series to form a high voltage inverter for each phase of a multi-phase system. In the exemplary H-bridge multilevel inverter topology 80 illustrated in FIG. 3, two such single phase inverters 82 and 84 are connected in series to form a single phase of a three-phase inverter. (The remaining two phases have a similar configuration and respective independent DC voltage sources.) The first single phase inverter 82 includes a DC voltage source 86 and four inverter switching devices 88-91 connected in an H-bridge configuration across the DC voltage source 86. The second H-bridge inverter 84 includes a DC voltage source 92 and four inverter switching devices 94-97 connected together in an H-bridge configuration across the voltage source 92. The node A between switching devices 88 and 89 of a second leg of the first H-bridge inverter 82 is the output node for this phase of the multi-phase inverter. The node between inverter switching devices 96 and 97 of a first leg of the second H-bridge inverter 84 is connected to the neutral line of the multi-phase inverter. The first 82 and second 84 H-bridge inverters are connected together at a node between switching devices 90 and 91 of a first leg of the first H-bridge inverter 82 and a node between switching devices 94 and 95 of a second leg of the second H-bridge inverter 84. Each of the inverter switching devices 88-91 and 94-97 may be implemented as an IGBT switching device 98 and a diode 100 connected in anti-parallel with the IGBT switching device 98. The voltages across the DC voltage sources 86 and 92 are equal. It may be seen that the H-bridge multilevel inverter 80 is capable of producing five distinct voltage levels (+/-2V, +/-V, and 0V) at output node A. For example, with switching devices 97, 94, 91, and 88 closed, an output voltage level of +2V is provided at output node A. Other switching combinations are employed to provide the other voltage levels at the output node A. Thus, the H-bridge multilevel inverter 80 may be controlled to provide a five level output voltage waveform 102, as illustrated in FIG. 4. (Waveform 104 is the desired AC signal to be synthesized.)
The advantage of the H-bridge multilevel inverter topology is that its modular configuration provides flexibility for easy expansion of the number of levels without introducing undue complexity in the power circuit. This topology requires the same number of switches as in a diode clamped inverter topology to achieve a given number of (odd) voltage levels. However, the H-bridge multilevel inverter topology requires multiple dedicated DC buses, which makes it an expensive solution. On the other hand, since the DC bus voltage sources are independent, the problem of capacitor voltage balancing is eliminated.